1. Field of the Invention
The present invention relates to method and apparatus for designing a three-dimensional integrated circuit formed in such a manner that a semiconductor circuit is laid out on a plurality of stacked layers.
2. Description of the Related Art
In recent years, the Si substrate via (vertical interlayer interconnect) technique has been proposed (see, e.g., Japanese Patent No. 2863613). According to the technique, wirings between a plurality of stacked chips are made by the Si substrate vias formed in a substrate, instead of bonding wires. The Si substrate vias can make conduction paths between a plurality of stacked substrates, so that a two-dimensional chip area is largely reduced.
The use of the foregoing Si substrate via can realize a stacked module of system LSIs, including memories, such as SRAM and DRAM, and a processor. Therefore, interconnect delay can be greatly reduced. A via diameter of a through-hole for forming the Si substrate via is reduced to fall in a range from several μm to several tens of μm. As a result, several thousands to several ten thousands of substrate via are formed in the whole chip.
On the other hand, according to a conventional circuit layout design system, circuits are merely laid out two-dimensionally. For this reason, in order to form a three-dimensional circuit layout using via, a circuit layout design system adaptable to the three-dimensional circuit layout must be developed. This is a factor of requiring huge cost and much time. In particular, the three-dimensional circuit layout must be optimized to develop an application-specific integrated circuit (ASIC). Thus, cost and time are further taken to develop the circuit layout design system. Moreover, according to the foregoing Patent Publication, routing between surfaces three-dimensionally laid is manually done. For this reason, design is troublesome, and the design cost increases.
In order to solve the foregoing problem, it is desired to realize a new method and apparatus for designing a three-dimensional integrated circuit, using conventional two-dimensional layout data. Specifically, the design cost and time are economized, and a long interconnecting portion is reduced, and thereby, it is possible to design a three-dimensional integrated circuit having excellent performance.